Thesis

  • David C. Walter, "Verification of analog and mixed-signal circuits using symbolic methods," PhD Thesis, University of Utah, August, 2007. (pdf)

Journal Articles

  • S. Little, D. Walter, C. Myers, R. Thacker, S. Batchu, and T. Yoneda, "Verification of analog/mixed-signal circuit using labeled hybrid Petri nets," in IEEE Transactions on Computer-Aided Design (TCAD), Vol. 30, No. 4 (April, 2011): 617–630. (link)
  • S. Little, D. Walter, K. Jones, C. Myers, A. Sen, "Analog/mixed-signal circuit verification using models generated from simulation traces," to appear in International Journal of Foundations of Computer Science (IJFCS), Vol. 21, No. 2 (2010): 191–210.
  • D. Walter, S. Little, C. Myers, N. Seegmiller, T. Yoneda, "Verification of analog/mixed-signal circuits using symbolic methods," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), December, 2008, 27(12): 2223–2235. (link)
  • C. Myers, R. Harrison, D. Walter, N. Seegmiller, and S. Little, "The case for analog circuit verification," in Electronic Notes in Theoretical Computer Science (ENTCS), June, 2006, 153(3): 53–63. (link)
  • H. Zheng, C. Myers, D. Walter, S. Little, and T. Yoneda, "Verification of timed circuits with failure directed abstractions," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), March, 2006, 25(3): 403–412. (pdf)

Conference Papers

  • S. Little, D. Walter, K. Jones, and C. Myers, "Analog/mixed-signal circuit verification using models generated from simulation traces," in Automated Technology for Verification and Analysis (ATVA), October, 2007, pp. 114–128. (pdf)
  • D. Walter, S. Little, and C. Myers, "Bounded model checking of analog and mixed-signal circuits using an SMT solver," in Automated Technology for Verification and Analysis (ATVA), October, 2007, pp. 66–81. (pdf)
  • D. Walter, S. Little, N. Seegmiller, C. Myers, and T. Yoneda, "Symbolic model checking of analog/mixed-signal circuits," in Asia and South Pacific Design Automation Conference (ASPDAC), January, 2007, pp. 316–323. (pdf)
  • S. Little, N. Seegmiller, D. Walter, C. Myers, and T. Yoneda, "Verification of analog/mixed-signal circuits using labeled hybrid Petri nets," in International Conference on Computer-Aided Design (ICCAD), November, 2006, pp. 275–282. (pdf)
  • S. Little, D. Walter, C. Myers, and T. Yoneda, "Verification of analog and mixed-signal circuits using timed hybrid Petri nets," in Second International Symposium on Automated Technology for Verification and Analysis (ATVA), 2004, pp. 426–440. (pdf)
  • H. Zheng, C. Myers, D. Walter, S. Little, and T. Yoneda, "Verification of timed circuits with failure directed abstractions," in IEEE International Conference on Computer Design (ICCD), 2003, pp. 28–35. (pdf)

Workshops

  • D. Walter, S. Little, N. Seegmiller, and C. Myers, "Symbolic model checking of hybrid Petri nets using BDDs," at SRC Student Symposium, October, 2006.
  • C. Myers, R. Harrison, D. Walter, N. Seegmiller, and S. Little, "The case for analog circuit verification," in The Workshop on Formal Verification of Analog Circuits (FAC), April, 2005. (pdf)
  • D. Walter, S. Little, N. Seegmiller, and C. Myers, "Symbolic model checking of hybrid Petri nets using BDDs," at TECHCON 2005, October, 2005.