Professional Background

I completed a Ph.D. in Computer Science at the University of Utah School of Computing in the summer of 2007. As a graduate student, I worked in the Myers Research Group. The overall goal of our work was to develop a framework and tools to allow for the efficient verification of analog and mixed–signal systems. I also completed undergraduate degrees in Computer Science and Computer Engineering at the University of Utah in 2001.

In May of 2007 I departed for the Philippines to become a U.S. Peace Corps Volunteer for 27 months. My position in the U.S. Peace Corps is as a teacher in information technology and English. I will be returning to the United States in August of 2009.

While in the Philippines, the best way to contact me is by e–mail using the Contact Me link at the bottom of this page. I try to respond to communications quickly.

Résumé and CV

The following are links to public versions of my résumé and CV. For complete versions, please contact me.

  • Résumé. Last updated April 24, 2007. (pdf)
  • CV. Last updated April 24, 2007. (pdf)

Selected Publications

  • D. Walter, S. Little, and C. Myers, “Bounded model checking of analog and mixed–signal circuits using an SMT solver,” in Automated Technology for Verification and Analysis (ATVA), October, 2007, pp. 66–81. (pdf)
  • David C. Walter, “Verification of analog and mixed–signal circuits using symbolic methods,” PhD Thesis, University of Utah, August, 2007. (pdf)
  • D. Walter, S. Little, N. Seegmiller, C. Myers, and T. Yoneda, “Symbolic model checking of analog/mixed–signal circuits,” in Asia and South Pacific Design Automation Conference (ASPDAC), January, 2007, pp. 316–323. (pdf)
  • S. Little, N. Seegmiller, D. Walter, C. Myers, and T. Yoneda, “Verification of analog/mixed–signal circuits using labeled hybrid Petri nets,” in International Conference on Computer–Aided Design (ICCAD), November, 2006, pp. 275–282. (pdf)
  • C. Myers, R. Harrison, D. Walter, N. Seegmiller, and S. Little, “The case for analog circuit verification,” in Electronic Notes in Theoretical Computer Science (ENTCS), June, 2006, 153(3): 53–63. (link)
  • H. Zheng, C. Myers, D. Walter, S. Little, and T. Yoneda, “Verification of timed circuits with failure directed abstractions,” in IEEE Transactions on Computer–Aided Design of Integrated Circuits and Systems (TCAD), March, 2006, 25(3): 403–412. (pdf)
  • S. Little, D. Walter, C. Myers, and T. Yoneda, “Verification of analog and mixed–signal circuits using timed hybrid Petri nets,” in Second International Symposium on Automated Technology for Verification and Analysis (ATVA), 2004, pp. 426–440. (pdf)